1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof having an improved contact in a contact hole through an interlayer insulating layer. More particularly, the present invention relates to a semiconductor device in which an isolating region for active region in the semiconductor substrate is subject to less erosion even when the interlayer contact hole falls thereon.
2. Background Art
The conventional semiconductor device has the contact structure as shown in a cross sectional view in FIG. 18. It is shown that the semiconductor substrate 1 has a P-well 2, an N-well 3, and an isolation region (isolation oxide film) 4 formed thereon. There is formed an active semiconductor element consisting of a gate oxide film 5, a gate electrode 6, a sidewall 7, an N+ diffusion layer 8, and a high-melting silicide layer 9. There is formed an interlayer oxide film 10, through which a contact hole 11 penetrates for interlayer connection via an aluminum electrode 14. It is noted that the isolation region (isolation oxide film) 4 has an eroded portion 12 which is formed when the contact hole 11 is formed. Further, a diffusion layer 13 is formed to prevent current leakage.
The above-mentioned conventional semiconductor device is manufactured according to the process shown in sectional views in FIG. 19.
The conventional process starts with deposition of an oxide film 19 and a nitride film 20 on a substrate 1, as shown in FIG. 19(a), which is followed by selective etching. With the etched part filled by an oxide film, the entire surface of the wafer is polished by CMP method (chemical mechanical polishing) so as to form an isolating oxide film 4. The nitride film 20 and the oxide film 19 are removed afterwards.
Then, the substrate 1 is doped with an N-type impurity and P-type impurity by ion implantation so as to form a P-well 2 and an N-well 3, as shown in FIG. 19(b).
In the next step, the entire surface of the wafer is oxidized so as to form a gate oxide film 5, on which is deposited polysilicon by CVD method. This step is followed by selective etching to form a gate electrode 6, as shown in FIG. 19(c).
Subsequently, on the entire surface is deposited an oxide film, which undergoes etch-back so as to form a sidewall 7 on the side of the gate electrode 6. An N+ diffusion layer (impurity region) 8 is formed by implantation of an N-type impurity. The entire surface of the wafer undergoes sputtering with a high-melting metal, which is selectively made into a high-melting silicide layer 9 by lamp annealing.
In the subsequent step shown in FIG. 19(d), an interlayer oxide film 10 is deposited by CVD and a contact hole 11 is formed by selective etching. This etching should be carried out such that the depth of etching exceeds 120% of the thickness of the interlayer oxide film 10, taking into account the variation of the thickness of the interlayer oxide film 10 and the fluctuation of the etching rate.
Next comes ion implantation of an N-type impurity into the bottom of the contact hall 11 and formation of a diffusion layer 13 to prevent current leakage.
The entire process is completed by sputtering with materials of barrier metal layer and aluminum and subsequent selective etching to form a barrier metal layer 28 and an aluminum electrode 14. (See FIG. 18.)
The above-mentioned conventional semiconductor device is constructed as shown in a sectional view in FIGS. 20(a) and 20(b) which are presented to explain how it works.
As FIG. 20(a) shows, the conventional semiconductor device has a contact 14 which is made such that the depth D of the eroded portion 12 in the isolating oxide film 4 is greater than the diffusion depth Xj of the N+ diffusion layer 8. An undesirable consequence of this is that a large amount of current flows through not only the primary current path AA but also the secondary current path BB. In order to cope with this situation, there is formed a diffusion layer 13 to block current leakage, as shown in FIG. 20(b).
Forming a diffusion layer 13 needs the steps of photolithography and ion implantation. This poses an increase in the number of steps. Moreover, the diffusion layer 13 to prevent current leakage increases the junction capacitance between the N+ diffusion layer 8 and the P-well 2, as shown in FIG. 20(b). This leads to a slow down of circuit speeds.
The present invention was completed to address the above-mentioned problem involved in the prior art technology. Accordingly, it is an object of the present invention to provide an improved semiconductor device and a manufacturing method thereof, eliminating the necessity of forming the diffusion layer for leakage prevention and hence requiring a less number of processing steps as well as having a reduced capacitance between the impurity region (N+ diffusion layer) and the semiconductor substrate (P-well).
According to one aspect of the present invention, a semiconductor device comprises a semiconductor substrate and a plurality of impurity regions formed on the surface of said semiconductor substrate. An isolating region is formed on the surface of said semiconductor substrate to electrically isolate said impurity regions from each other. An interlayer insulating film is formed on the surface of said silicon semiconductor substrate. A contact hole is provided to penetrate said interlayer insulating film and to reach said impurity region and said isolating region across the boundary thereof. A contact material is filled in said contact hole. Further, said isolating region includes a material having substantially high etching selectivity than said interlayer insulating film, and the bottom of said contact hole extends into said isolating region to the depth less than the depth of said impurity region.
In the semiconductor device, said semiconductor substrate may be composed of silicon, said interlayer insulating film may be composed of silicon dioxide, and said isolating region may be composed of silicon nitride.
In the semiconductor device, said semiconductor substrate may be composed of silicon, said interlayer insulating film may be composed of silicon dioxide, and said isolating region is composed of double layer structure of a silicon nitride layer and a silicon oxide layer formed beneath said silicon nitride layer.
According to another aspect of the present invention, in a semiconductor device, said isolating region may includes a material having substantially high etching selectivity than said interlayer insulating film at least at the interface with said active regions which includes an impurity region.
In the semiconductor device, said semiconductor substrate may be composed of silicon, said interlayer insulating film may be composed of silicon dioxide, and said material in said isolating region may be composed of silicon nitride.
According to one aspect of the present invention, a semiconductor device comprises an intermediate film formed on the entire surface of said semiconductor substrate and an interlayer insulating film formed on said intermediate film. A contact hole is provided which penetrates said interlayer insulating film and said intermediate film and reaches said impurity region and said isolating region across the boundary thereof and a contact material is filled in said contact hole. Further, said intermediate film includes a material having substantially high etching selectivity than said interlayer insulating film, and the bottom of said contact hole extends into said isolating region to the depth less than the depth of said impurity region.
In the semiconductor device, said semiconductor substrate may be composed of silicon, said interlayer insulating film may be composed of silicon dioxide, and said material in said intermediate film may be composed of silicon nitride.
In the semiconductor device, said semiconductor substrate may be composed of silicon, said interlayer insulating film may be composed of silicon dioxide, and said intermediate film may be composed of double layer structure of a silicon nitride layer and a silicon oxide layer formed beneath said silicon nitride layer.
In the semiconductor device, said semiconductor substrate may be composed of silicon, said interlayer insulating film may be composed of silicon dioxide, and said intermediate film may be composed of a double layer structure of a polysilicon layer and a silicon dioxide layer formed beneath said polysilicon layer.
In the semiconductor device, said impurity region may have a projection intruding into said isolating region, and said contact hole reaches said impurity region in said projection and said isolating region adjacent on both side of said projection.
Other and further objects, features and advantages of the invention will appear more fully from the following description.